The present invention relates to a method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices.
The need is currently increasingly felt to integrate on a single silicon chip signal processing logics and high-voltage components which operate efficiently and reliably. In particular, in these structures the junctions where the electric field is strongest should resist to the applied voltages to prevent avalanche breakdowns of the same junctions.
In the case of bipolar-technology integrated circuits of the type comprising an insulated drive transistor and a vertical power transistor, the problem of voltage withstanding ability has been met by using a planar field plate obtained by extending the metalizations of suitable regions on thick oxide beyond the junctions to be protected. An example of this solution is indicatively shown in FIG. 1, illustrating a cross section through a silicon wafer accommodating an insulated NPN drive transistor 1 and a vertical NPN power transistor 2. In detail, as can be seen, the structure comprises a substrate 5 of the N.sup.+ type connected as a collector of the power transistor 2, an epitaxial layer 6 of the N.sup.- type, a region 7 of the P.sup.+ type constituting the base of the transistor 2 and forming, with the layer 6, a junction 21, as well as an emitter region 8 of the N.sup.+ type provided inside the region 7. In the layer 6, the P type buried layer 9 is furthermore formed which extends up to the upper surface of the circuit by means of P.sup.+ type insulation portions 10 so as to separate the transistor 1 from the remaining area. In particular, inside the isolation 9, 10, an N.sup.- type collector region 11 is enclosed, and the P type base region 12 and the N.sup.+ type, respectively collector and emitter, regions 13 and 14 are formed. The structure is completed by the oxide layer 15 extending selectively on the upper main surface of the device, the collector 16, emitter 17, base 18 metal layers of the drive transistor 1, and the emitter 19 and base 20 metal layers of the power transistor 2. In this structure, the junctions most subject to the risk of breakdown and which are therefore to be protected are constituted by the base/collector junction 21 between the layers 6 and 7 of the power device 2 and the isolation/collector junction 22 between the regions 10 and 6 for the isolation regions. Accordingly, on the surface of the device field plates 23 and 20 have been provided for junction 22 and for junction 21, respectively, while the short-circuit metalization or metal layer 24 between the isolation 10 and the base 7 also constitutes a field plate.
It is known (see, e.g., F. Conti, M. Conti "Surface breakdown in silicon planar diodes equipped with field plate", Solid State Electronics, 1972, Vol. 5, pages 93-105) that this kind of solution has a limited efficiency because of the high electric field induced on the surface of the silicon proximate to the termination of the same field plate.
Solutions using the field plate have also been used in the case of integrated circuits produced in MOS technology. A known solution, integrating a CMOS drive device 40 with a power DMOS transistor 41 is illustrated by way of example in FIG. 2. This figure depicts the N.sup.+ type layer 30 connected as a drain D of the DMOS 41 and the N.sup.- epitaxial layer 31. Inside the layer 31, the P type buried layer 32 is provided, which is connected to the P.sup.+ type isolation regions 32', which in turn enclose the N.sup.- type epitaxial pocket 33, constituting the body of the P-channel MOS transistor of the CMOS 40. Inside the pocket 33, the drain region 34 and source region 35 of the P-channel transistor of the CMOS are provided, together with the N.sup.+ type region 36 as short circuit between the body and the source, and with the P.sup.- type P-well region 37 constituting the body of the N-channel transistor of the CMOS 40. Inside the region 37, therefore, the drain 38 and source 39 regions of the N.sup.+ type are formed. In turn, the power DMOS 41 comprises the P type body regions 55 in which the N.sup.+ type source regions 56 are provided. On the outer face of the device, the portions 46 of the isolation oxide layer are furthermore visible, together with metalization 49 connected to the left insulation region 32', provided on the polysilicon biplanar electrode 45 and constituting a triplanar field plate, the drain 50 and source 51 metalization of the P-channel transistor of the CMOS and drain 52 and source 53 metalizations of the N-channel transistor of the CMOS. The figure furthermore shows the gate electrodes 47 and 48 of the P and N channel transistors of the CMOS and, for the power transistor 41, the source metalization 58 which extends to the isolation region 32' and constitutes a planar field plate, the source metalization 59, also provided above the biplanar polysilicon electrode 45' and constituting therewith a triplanar field plate, as well as the gate electrode 57. In this case the junctions to be protected are represented by the body/drain junction 60 between the layers 55 and 31 of the power device and the isolation/drain junction 61 between the regions 32' and 31. In this case the field plate is triplanar due to the presence of the two levels of polysilicon and of one level of metalization.
This known solution, though it offers greater efficiency with respect to the previous one, still gives rise, in this case, to a significant increase in the surface electric field at the transitions between the different levels of the field plate, with the consequent risk of degrading the characteristics of the circuit.
In order to reduce the surface electric field and to make it more uniform, border solutions have also been proposed (see Viktor A. K. Temple "Junction Termination Extension (JTE), a new technique for increasing avalanche breakdown voltage and controlling surface electric fields in P-N junctions", Int. Electron Devices Meeting, 1977, New York, p. 423-426; B. J. Baliga "High-voltage device termination technique. A comparative review", IEE Proc. Vol. 129, Pt I, No. 5, 10/1982; Shikayuki Ochi et al., "Computer Analysis of Breakdown Mechanism in planar power MOSFET", IEEE Trans. on Electron Devices, Vol. ED-27, No. 2, 2/1980) such as the one illustrated in FIG. 3, which represents the cross section through a silicon wafer integrating a vertical N-channel DMOS transistor, using this solution. As can be seen, in a structure comprising an N.sup.+ type substrate 65 and an N.sup.- type epitaxial layer 66 comprising body regions 67, the structure indicated with the reference numeral 68 is provided, with P type conductivity. This structure 68 comprises a first portion 68' which forms a body and two regions 68" and 68"' again with P type conductivity but with a smaller surface concentration of doping impurities. In practice, the regions 68', 68" and 68"' extend with decreasing thickness towards the interior of the DMOS device. This solution is particularly advantageous and allows to achieve efficient and reliable high voltage devices. A process according to this technique for obtaining in the same chip a CMOS and a DMOS device is shown in FIG. 6a-6d. The starting structure according to this prior method, shown in FIG. 6a, comprises a double epitaxial layer 70 of the N.sup.- conductivity type, grown on an N.sup.+ substrate, not illustrated in the figure, and accommodating a P type buried layer 71. In particular, according to the prior art, the initial step comprises a boron implant only to provide the P-well. For this purpose, a photoresist layer 110 is provided which has a single opening or window on the surface of the device where the P-well is to be formed. Subsequently, according to this method (as can be seen in FIG. 6b), boron atoms are implanted to form the insulation of the CMOS. Only thereafter, as illustrated in FIG. 6c, boron atoms are implanted (indicated symbolically by the arrows 112) to obtain first regions of the desired border structure. For this purpose, above the device main surface an oxide layer 111 is provided, having suitable windows for the passage of the boron atoms which thus accumulate in the thin layers 113 and 114.
Finally, according to the prior art, boron is implanted (arrows 117) to provide the outermost ring or border region 115 and 116. As can thus be seen, according to the prior art, the different portions of the border extension structure of the DMOS and the CMOS devices are grown in different, subsequent steps, so that it is necessary to perform a high number of photolithographic steps, which increase the manufacturing costs.